Efficient Fixed Width Adder Tree Design | Final Year VLSI IEEE Projects in Hyderabad

TO PURCHASE OUR PROJECTS IN ONLINE CONTACT : TRU PROJECTS WEBSITE : www.truprojects.in MOBILE : 9676190678 MAIL ID : info@truprojects.in ABSTRACT : Conventionally, fixed-width adder-tree (AT) design is obtained from the full-width AT design by employing direct or post-truncation. In direct-truncation, one lower order bit of each adder output of full-width AT is post-truncated, and in the case of post-truncation, {p} lower order-bits of final-stage adder output are truncated, where p = log2N and N is the input-vector size. Both these methods does not provide an efficient design. In this brief, a novel scheme is presented to obtain fixed-width AT design using truncated input. A bias estimation formula based on probabilistic approach is presented to compensate for the truncation error. The proposed fixed-width AT design for input-vector sizes 8 and 16 offers (37%, 23%, 22%) and (51%, 30%, 27%) area-delay product saving for word-length sizes (8, 12, 16), respectively, and calculates the output almost with the same accuracy as the post-truncated fixed-width AT, which has the highest accuracy among the existing fixed-width AT. Further, we observed that Walsh–Hadamard transform based on the proposed fixedwidth AT design reconstruct higher-texture images with higher peak signal-to-noise ratio (PSNR) and moderate-texture images with almost the same PSNR compared to those obtained using the existing AT designs. Besides, the proposed design creates an additional advantage to optimize other blocks appear at the upstream of the AT in a complex design.